1. Field of the Invention
The present invention relates to electronic hearing devices and electronic systems for sound reproduction. More particularly, the present invention relates to the field to delta-sigma digital-to-analog data converters (xe2x80x9cDACsxe2x80x9d), and specifically to converting the digitally processed sound in a hearing aid to an analog waveform. The present invention can be used in any digital signal processing device, including, without limitation, hearing aids, telephones, assistive listening devices, and public address systems.
2. The Background Art
An essential part of a delta-sigma digital to analog converter (xe2x80x9cDACxe2x80x9d) is an interpolator which increases the sample rate of the digital signal being converted. From a theoretical standpoint, interpolator algorithms and interpolator structures are well documented in the digital signal processing literature. As is know to those skilled in the art, most interpolators utilize a polyphase structure with either a finite impulse response (xe2x80x9cFIRxe2x80x9d) or infinite impulse response (xe2x80x9cIIRxe2x80x9d) filter. FIR and IIR filter design is not discussed in detail herein, so as not to overcomplicate the present disclosure. However, the topic is extensively treated in books such as xe2x80x9cMultirate Systems and Filter Banks,xe2x80x9d by P. P. Vaidyanathan (Prentice Hall, 1993).
Because they require adder and multiplier circuitry, most theoretical interpolator structures, taken directly, are computationally too complex to implement in the amount of circuitry available in certain small-size, low-power applications such as hearing aids. In such applications, the amount of silicon area to implement the interpolator circuit must be kept to a minimum, and hence the interpolator must be implemented without a multiplier.
Unfortunately, digital interpolator algorithms and structures capable of achieving design requirements in a computationally efficient and circuit area efficient manner so as to be suitable for use in small-size, low-power applications are not currently available.
Thus, the present invention provides an interpolator algorithm and structure suitable for use in small-size, low-power applications. The interpolator algorithm and structure according to aspects of the present invention achieves the design requirements in a computationally efficient and circuit area efficient manner. As part of a larger and more complex signal processing system, it facilitates providing better sound quality to end customers. Embodiments of the present invention can be used in any application where using a multiplierless interpolator is desired. These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and in the associated figures.
A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (xe2x80x9cICxe2x80x9d) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (xe2x80x9cIIRxe2x80x9d) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (xe2x80x9cZOHxe2x80x9d) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.